Dynamic object-level code translation for improved performance of a computer processor
US8200987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2008 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Jan 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.