Selective power reduction of memory hardware
US8200999B2 · kind B2 · utility
3Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2008 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Dec 9, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. An energy exchange threshold for the computer system is set, and management of one or more of the hardware memory devices is employed when the computer system exceeds an energy exchange threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.