Circuit for preventing computer power down sequence failure
US8201003B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Sep 10, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Nov 3, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for confirming a correct computer power down sequence includes a Southbridge chip, a first switching transistor circuit, and a second switching transistor circuit. The first switching transistor circuit receives a power good signal. The second switching transistor circuit receives a S3 sleep signal. The first and second switching transistor circuits have a common output node coupled to the Southbridge chip. During a computer power down sequence, the S3 sleep signal is set from high to low before than the power good signal, and the S3 sleep signal is active and fed to the Southbridge chip, thereby quickly providing a low level power good signal to the Southbridge chip and confirming the power down sequence is correct.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.