Entry/exit control to/from a low power state in a complex multi level memory system
US8201004B2 · kind B2 · utility
8Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Sep 14, 2007 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Dec 12, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic modules during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.