Timing point selection for a static timing analysis in the presence of interconnect electrical elements
US8201120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2010 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.