Patent · US Active

Early estimation of power consumption for electronic circuit designs

US8201121B1 · kind B1 · utility

13Cited by

2References

23Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Ranganathan Sankaralingam · Fremont, US
Yan Meng · Shanghai, CN

Key dates

Filing date	May 28, 2008
Grant date	Jun 12, 2012
Priority date	—
Expiry date	Jun 7, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a method of designing integrated circuits is disclosed. The method includes determining a power correction factor for a subset of partitions of circuits in an integrated circuit design; determining a gross power consumption estimate for all partitions of circuits in the integrated circuit design without synthesizing the entire integrated circuit design; and improving the accuracy of the gross power consumption estimate using the power correction factor to generate a reasonably accurate power consumption estimate for the entire integrated circuit design prior to substantially full circuit synthesis thereof.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.