Method of manufacturing transistor

US8202782B2 · kind B2 · utility

Assignee

• NXP B.V. · NL

Inventors

• Philippe Meunier-Bellard · Steenokkerzeel, BE
• Anco Heringa · Eindhoven, NL
• Johannes Josephus Theodorus Marinus Donkers · Valkenswaard, NL

Key dates

• Filing date: Aug 29, 2008
• Grant date: Jun 19, 2012
• Expiry date: Feb 4, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/90

Abstract

A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).