Opportunistic timing control in mixed-signal system-on-chip designs
US8203357B2 · kind B2 · utility
2Cited by
2References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 4, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Feb 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1225
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.