Semiconductor memory device and method of programming the same
US8203883B2 · kind B2 · utility
8Cited by
0References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2010 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Feb 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a semiconductor memory device including a cell array with NAND strings arranged therein, wherein the device has such a program mode that bit lines and cell's channels of the NAND strings coupled thereto are initially charged in accordance with program data, and then program voltage is applied to memory cells selected in the cell array. In the program mode, a certain bit line and a program-inhibited cell's channel coupled thereto, which are initially charged to Vdd, are boosted to be higher than Vdd by capacitive coupling from the cell source line prior to the program voltage application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.