High-performance digital image memory allocation and control system
US8205020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Jul 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described that facilitate mitigating processor overload and reducing memory waste during image compression. Clients requesting memory allocation are assigned a direct memory access (DMA) channel to which DMA memory blocks are allocated for use during image compression. As each DMA block is used by its channel, the DMA block generates an interrupt message that is counted by a DMA counter and may be optionally processed by the CPU. If the number of interrupts being processed exceeds a first threshold, then memory block size is increased to reduce processor load. If the number of interrupts is below a second, lower threshold, then block size is decreased to reduce and amount of unused but allocated memory in the final block allocated to the channel a compressed image file. Fixed DMA block size may also be used and any DMA block may be programmed to generate an interrupt indicating a memory usage threshold has been crossed and that additional DMA memory blocks should be allocated to continue compression beyond the number of DMA blocks initially allocated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.