Patent · US Active

Non-volatile memory and controlling method thereof

US8205036B2 · kind B2 · utility

4Cited by
4References
5Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 24, 2009
Grant dateJun 19, 2012
Priority date
Expiry dateFeb 6, 2030

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2212/7211
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.