Satisfying memory ordering requirements between partial writes and non-snoop accesses
US8205045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2008 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Jun 25, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for preserving memory ordering in a cache coherent link based interconnect in light of partial and non-coherent memory accesses is herein described. In one embodiment, when a conflict associated with a partial memory access, such as a partial write, is detected, a write-back phase is inserted at the conflict phase to write-back the partial data to a home agent. Examples messages to initiate a write-back phase at a conflict phase include: an Acknowledge Conflict Write-back message to acknowledge a conflict and provide a write-back marker at the beginning of the conflict phase, a write-back marker message before the conflict phase, a write-back marker message within the conflict phase, a write-back marker message after the conflict phase, and a postable message after the conflict phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.