Method and system for integrated pipeline write hazard handling using memory attributes
US8205057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Aug 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock cycle before data. The pre-computed memory management unit policy is registered and used for controlling a pipeline stall to ensure that a non-bufferable write is pipeline-protected, so that no non-bufferable location is bypassed from within the pipeline, and so that a subsequent non-bufferable read will get data from a final destination. A read request is bypassed only after a corresponding write request is updated in a write pending buffer. The write request is decoded with the write request aligned to data. The write request is registered in the write pending buffer. Arbitration logic is allowed to force the pipeline stall for a region that will have a write conflict. Read requests are stalled to protect against write hazards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.