Error corrector with a high use efficiency of a memory
US8205133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Apr 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2020/1836
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An error corrector with a high use efficiency of a memory includes a memory, a bus device, an input buffer and an error correction module. The memory stores data. The bus device controls a memory access. The input buffer receives and temporarily stores a coded blockcode data, and writes the coded blockcode data in the memory through the bus device. The error correction module reads the coded blockcode data in the memory through the bus device and decodes it in rows and columns to thereby obtain decoded data and check bytes. The error correction module writes the decoded data in the memory through the bus device and discards the check bytes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.