Multi-layer cyclic redundancy check code in wireless communication system
US8205143B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2011 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Dec 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0065
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communication device is disclosed. The device is configured to generate a first block of first cyclic redundancy check (CRC) parity bits on a transport block wherein the first block of CRC parity bits is based on a first generator polynomial, to attach the first block of CRC parity bits to the transport block and to segment the transport block into multiple code blocks. The processor is also configured to generate a second block of CRC parity bits on each code block wherein each of the second blocks of CRC parity bits is based on a second generator polynomial that is different than the first generator polynomial. The first and second generator polynomials have a common degree. A second block of CRC parity bits is attached to each code block, and the code blocks are concatenated after channel encoding.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.