High-speed add-compare-select (ACS) circuit
US8205145B2 · kind B2 · utility
3Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2008 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Apr 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed add-compare-select (ACS) circuit for a Viterbi decoder or a turbo decoder has a lower critical path delay than that achievable using a traditional ACS circuit. According to one embodiment of the invention, the path and branch metrics are split into most-significant and least-significant portions, such portions separately added in order to reduce the propagation delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.