Integrated circuit modeling method and framework tool
US8205174B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 17, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit modeling method 100 implementable on computer, which has an executable software model 145 having modules 140 of reusable functional cores 105 coded in a high level language and a virtual platform of the integrated circuit employable in an architecture exploration step 115. A modeling library of modules coded in high level languages and hardware level languages are provided and instantiated according to user input in a functional verification step 120 having a co-simulation environment, with interface code 170 between modules automatically generated by an interface generator 130 based on a two dimensional data array of hardware specification inputs 205, the interface code 170 further interfacing with wrappers engaged between high and hardware level language modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.