Patent · US Active

Automatic synthesis of clock distribution networks

US8205182B1 · kind B1 · utility

66Cited by

35References

25Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Radu Zlatanovici · Oakland, US
Christoph Albrecht · San Jose, US
Saurabh Kumar Tiwary · Berkeley, US

Key dates

Filing date	Aug 22, 2008
Grant date	Jun 19, 2012
Priority date	—
Expiry date	Jul 24, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F2117/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.