Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby
US8207033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2009 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Sep 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02636
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.