3D polysilicon diode with low contact resistance and method for forming same
US8207064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2009 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Jan 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
Abstract
A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.