Phase locked loop and 3-stage frequency divider
US8207794B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 5, 2010 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Oct 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/191
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The phase locked loop has a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal. The 3-stage frequency divider comprises three cascaded frequency dividers with different rangers of operating frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.