Patent · US Active

Quick pixel rendering processing

US8207972B2 · kind B2 · utility

0Cited by

16References

48Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Jian Wei · Zhejiang, CN
Chehui Wu · San Diego, US
James M. Brown · San Diego, US

Key dates

Filing date	Dec 22, 2006
Grant date	Jun 26, 2012
Priority date	—
Expiry date	Mar 2, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06T15/005
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A three-dimensional (3D) graphics pipeline which processes pixels of sub-screens in the last stage (pixel rendering) in parallel and independently. The sub-screen tasks are stored in a list in a shared memory. The shared memory is accessed by a plurality of processing threads designated for pixel rendering. The processing threads seize and lock sub-screens tasks in an orderly manner and process the tasks to create the bit map for display on a screen. The tasks are created by dividing a display area having the vertex information superimposed thereon into M×N sub-screen tasks. Based on system profiling, M and N may be varied.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.