Graphics rendering pipeline that supports early-Z and late-Z virtual machines
US8207975B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2007 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Oct 4, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a graphics pipeline architecture for optimizing graphics rendering efficiency by advancing the Z-test operation prior to shading operations whenever possible, as determined by an upstream pipeline configuration unit. Each processing engine within the graphics pipeline maintains independent state for both early Z-mode and late Z-mode operations and also may maintain state common to both modes. The processing engines receive work transactions that include a Z-mode flag indicating whether the work transaction should be processed in late Z-mode or early Z-mode. The Z-mode flag is also used to dynamically route any resulting outbound data, so that the appropriate data flow for either early Z or late Z processing is dynamically constructed for each work transaction. The shader engine is advantageously relieved of unnecessary work whenever possible by discarding occluded samples whose z-values are not altered by shading operations before they enter the shader engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.