Array substrate with test shorting bar and display panel thereof
US8208084B2 · kind B2 · utility
92Cited by
5References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2009 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Oct 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136272
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.