SRAM yield enhancement by read margin improvement
US8208316B2 · kind B2 · utility
1Cited by
6References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 19, 2008 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Jun 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.