Semiconductor memory device and wear leveling method
US8209468B2 · kind B2 · utility
5Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 9, 2009 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | May 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The memory controller adjusts a period of managing the wear leveling with reference to the erasing counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.