System and method for achieving improved accuracy from efficient computer architectures
US8209597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Jan 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q40/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a system and method that can employ a low-instruction-per-second (lower-power), highly parallel processor architecture to perform the low-precision computations. These are aggregated at high-precision by an aggregator. Either a high-precision processor arrangement, or a low-precision processor arrangement, employing soft-ware-based high-precision program instructions performs the less-frequent, generally slower high-precision computations of the aggregated, more-frequent low-precision computations. One final aggregator totals all low-precision computations and another high-precision aggregator totals all high-precision computations. An equal number of low precision computations are used to generate the error value that is subtracted from the low-precision average. A plurality of lower-power processors can be arrayed to provide the low-precision computation function. Alternatively a plurality of SIMD can be used to alternately conduct low-precision computations for a predetermined number of operations and high-precision operations on a fewer number of operations. In an embodiment, aggregation can include summing values within predetermined ranges of orders of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.