Stacked NMOS DC-to-DC power conversion
US8212536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Dec 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0081
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments for at least one method and apparatus of generating a regulated voltage are disclosed. One method includes generating the regulated voltage though controlled closing and opening of a series switch element and shunt switch element, the series switch element being connected between a first voltage supply and a common node, and the shunt switch being connected between the common node and a second supply voltage. The series switch element includes an NMOS series switching transistor stacked with an NMOS series protection transistor, and closing the series switch element during a first period includes applying a switching gate voltage to a gate of the NMOS series switch transistor of the series switch element, wherein the switching gate voltage has a voltage potential of at least a threshold voltage greater than a voltage potential of the common node. The shunt switch element includes an NMOS shunt switching transistor stacked with an NMOS shunt protection transistor, and the shunt switch element is closed during a second period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.