Apparatus of low power, area efficient FinFET circuits and method for implementing the same
US8212584B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Sep 13, 2010 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Nov 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.