Interface converting circuit
US8212886B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 11, 2008 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | May 4, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N23/81
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interface converting circuit applied between a 3D de-interlace chip and a rear-end image compression chip. The interface converting circuit includes: a reducing FPS circuit, for dividing a first vertical synchronization signal to generate a second vertical synchronization signal, and converting a first horizontal synchronization signal to a second horizontal synchronization signal by masking the first horizontal synchronization signal according to the second vertical synchronization signal; a pixel clock multiplier, for multiplying a first pixel clock signal to generate a second pixel clock signal; and, a data-width converter, for converting an input signal with M bits data width, which is transmitted at a frequency of the first pixel clock signal by the 3D de-interlace chip, to an output signal with M/2 bits data width, which is transmitted at a frequency of the second pixel clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.