Variation-tolerant word-line under-drive scheme for random access memory
US8213257B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 9, 2010 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Random Access Memory (RAM) is provided. The RAM includes a plurality of word-line drivers, at least a first tracking transistor and a second tracking transistor. Each word-line driver has an input node receiving a decoding signal, a power node receiving an operation voltage and a driving node driving a word-line. In an embodiment, the first tracking transistor has two channel terminal nodes respectively coupled to the driving node of one of the word-line driver and a channel terminal node of the second tracking transistor; wherein the first tracking transistor has electronic characteristics tracking those of a driving transistor of word-line driver, and the second tracking transistor has electronic characteristics tracking those of pass-gate transistor(s) in each cell of the RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.