Method and apparatus for implementing processor instructions for accelerating public-key cryptography
US8213606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2004 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Jun 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5318
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.