Processing long-latency instructions in a pipelined processor

US8214624B2 · kind B2 · utility

Assignee

• Imagination Technologies Limited · GB

Inventors

• Morrie Berglas · Schreiber, CA
• Yoong Chert Foo · London, GB

Key dates

• Filing date: May 23, 2007
• Grant date: Jul 3, 2012
• Expiry date: Dec 30, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3885
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

There are provided a method and a processor for processing a thread. The thread includes a plurality of sequential instructions. The plurality of sequential instructions include some short-latency instructions and some long-latency instructions and at least one hazard instruction. The hazard instruction requires one or more preceding instructions to be processed before the hazard instruction is processed. The method includes the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method.