Patent · US Active

Method and apparatus to achieve maximum outer level parallelism of a loop

US8214818B2 · kind B2 · utility

2Cited by

5References

12Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Li Liu · Taipei, TW
Buqi Cheng · San Jose, US
Gansha Wu · Beijing, CN

Key dates

Filing date	Aug 30, 2007
Grant date	Jul 3, 2012
Priority date	—
Expiry date	May 3, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F8/452
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, the present invention includes a method for constructing a data dependency graph (DDG) for a loop to be transformed, performing statement shifting to transform the loop into a first transformed loop according to at least one of first and second algorithms, performing unimodular and echelon transformations of a selected one of the first or second transformed loops, partitioning the selected transformed loop to obtain maximum outer level parallelism (MOLP), and partitioning the selected transformed loop into multiple sub-loops. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.