FinFET method and device

US8216894B2 · kind B2 · utility

Assignee

• NXP B.V. · NL

Inventor

• Robert James Pascoe Lander · Leuven, BE

Key dates

• Filing date: Jun 10, 2009
• Grant date: Jul 10, 2012
• Expiry date: Jun 10, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/024

Abstract

A finFET structure is made by forming a fin (14), followed by a gate stack of gate dielectric (16), metal gate layer (18), polysilicon layer (20) and silicon-germanium layer (22). The gate stack is then patterned, and source and drain implants formed in the fin (14) away from the gate. The silicon germanium layer (22) is selectively etched away, a metal deposited over the gate, and silicidation carried out to convert the full thickness of the polysilicon layer (20) at the top of the fin. A region of unreacted polysilicon (38) may be left at the base of the fin and across the substrate.