ESD protection device with vertical transistor structure
US8217421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2010 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Oct 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/711
Abstract
A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.