Single photon avalanche diodes
US8217436B2 · kind B2 · utility
6Cited by
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32Claims
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Key dates
| Filing date | Jul 7, 2009 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | May 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F30/225
Abstract
A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.