Patent · US Active

Method and circuit for DisplayPort video clock recovery

US8217689B2 · kind B2 · utility

1Cited by

8References

4Claims

0Family size

Assignee

Integrated Device Technology, Inc. · US

Inventors

Lu Yang · Fremont, US
Sibing Wang · Shanghai, CN
Xiaoqian Zhang · Shanghai, CN

Key dates

Filing date	Jan 19, 2010
Grant date	Jul 10, 2012
Priority date	—
Expiry date	Sep 4, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/16
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.