Adaptive digital phase locked loop
US8217696B2 · kind B2 · utility
3Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2009 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Aug 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1075
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In some embodiments, a digital PLL is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.