Minimizing tessellation of surfaces
US8217936B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2008 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Jan 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T17/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer-readable storage medium are disclosed for minimizing tessellation of surfaces. A first plurality of polygons may be generated, wherein the first plurality of polygons are adjacent to a plurality of exterior curves of a surface. Each of the first plurality of polygons comprises at least one outside edge approximating a portion of one of the exterior curves within a first flatness tolerance. A second plurality of polygons may be generated, wherein the second plurality of polygons are on the interior of the surface. Each of the second plurality of polygons comprises a plurality of inside edges approximating portions of interior curves of the surface within a second flatness tolerance. The first flatness tolerance may be smaller than the second flatness tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.