Patent · US Active

Apparatus and method for low touch cache management

US8219757B2 · kind B2 · utility

0Cited by

3References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Glenn J. Hinton · Portland, US
Dale Juenemann · North Plains, US
R. Scott Tetrick · Portland, US

Key dates

Filing date	Sep 30, 2008
Grant date	Jul 10, 2012
Priority date	—
Expiry date	Mar 10, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/222
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.