Interface processor
US8219789B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2007 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | May 8, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a processor comprising a first port operable to generate a first indication dependent on a first activity at the first port, and a second port operable to generate a second indication dependent on a second activity at the second port. The processor also comprises an execution unit arranged to execute multiple threads; and a thread scheduler connected to receive the indications and arranged to schedule the multiple threads for execution by the execution unit based on those indications. The scheduling includes suspending the execution of a thread until receipt of the respective ready signal. The first activity and the second activity are each associated with respective corresponding threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.