Two-level guarded predictive power gating
US8219833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2009 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Aug 30, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism is provided for two-level guarded predictive power gating of a set of units within the data processing system. A success determines whether a unit within the set of units is power gated during a monitoring interval. If the unit is power gated, the success monitor determines whether a count of idle cycles for the unit is below a breakeven point. If the count is above the breakeven point, the success monitor increments a success efficiency counter. If the count is below the breakeven point, the success monitor determines whether the unit needs to be woke up. If the unit needs to be woke up, the success monitor increments a harmful efficiency counter. If the value of the harmful efficiency counter is less than the value from the success efficiency counter, the success monitor enables power gating for the unit via a first-level power-gating mechanism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.