System and method of identifying and preventing security violations within a computing system
US8220045B2 · kind B2 · utility
14Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2004 |
| Grant date | Jul 10, 2012 |
| Priority date | — |
| Expiry date | Aug 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of identifying and preventing security violations within a computing system. Some exemplary embodiments may be a method comprising monitoring activity on a core bus coupled to a processor core (the processor core operating in a computing system), identifying activity on the core bus as a security violation, and preventing execution of an instruction within the processor core in response to the security violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.