Semiconductor device capable of reducing a contact resistance of a lower electrode and a contact pad and providing an align margin between the lower electrode and the contact pad
US8222715B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an insulation interlayer and an etch stop layer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed. A second contact pad penetrates the insulation interlayer and the etch stop layer and is connected to the first contact pad. The second contact pad protrudes from the etch stop layer. A pad spacer is provided between the second contact pad and the insulation interlayer. A lower electrode is provided on the etch stop layer and is connected to the second contact pad. A dielectric layer and an upper electrode are sequentially provided on the lower electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.