Fault tolerant asynchronous circuits
US8222915B2 · kind B2 · utility
5Cited by
21References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Apr 27, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.