Dynamic phase alignment
US8222920B2 · kind B2 · utility
2Cited by
6References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2009 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide methods and integrate circuits with dynamic phase alignment between an input data signal and a clock signal. In some embodiments, a sampling window of the input data signal may be determined and timing of the input data signal may be adjusted to enable the input data signal to be sampled within the sampling window. Other embodiments may be disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.