Time-domain measurement of PLL bandwidth
US8222961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2011 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Jan 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a device for determining closed loop bandwidth characteristic of a Phase Locked Loop (PLL) (52) comprising a voltage controlled oscillator (VCO) (53) controlled by means of a tuning voltage (Vtune) is disclosed. An embodiment of the invention compares the VCO tuning voltage (Vtune) to a low threshold voltage (Vlow) and a high threshold voltage (Vhigh), creating an oscillation of the VCO tuning voltage by offsetting the divider value such that the PLL (52) forces the tuning voltage (Vtune) towards the high threshold voltage (Vhigh) when the low threshold voltage (Vlow) is reached, and offsetting the divider value such that said PLL (52) forces the tuning voltage (Vtune) towards the low threshold voltage (Vlow) when the high threshold voltage (Vhigh) is reached, measuring the period of the oscillation between the high and the low threshold voltage of the VCO tuning voltage by counting the number of cycles of a reference clock signal (clk), and comparing the number of reference clock cycles to a reference number of clock cycles to determine the relative loop bandwidth of the PLL (52).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.