2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator
US8223053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2010 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | Sep 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sigma-delta modulator may have a plurality of capacitor pairs, a plurality of switches to couple any pair of capacitors from the plurality of capacitor pairs selectively to an input signal or a reference signal, and a control unit operable to control sampling through the switches to perform a charge transfer in two phases wherein any pair of capacitors can be selected to be assigned to the input signal or the reference signal, and wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically such that after a rotation cycle, each capacitor pair has been assigned a first predetermined number of times to the input signal, and has also been assigned a second predetermined number of times to the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.