Express virtual channels in a packet switched on-chip interconnection network
US8223650B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2008 |
| Grant date | Jul 17, 2012 |
| Priority date | — |
| Expiry date | May 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/101
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method, router node, and set of instructions for using express virtual channels in a component network on a chip. An input link 302 may receive an express flow control unit from a source node 102 in a packet-switched network via an express virtual channel 110. An output link 306 may send the express flow control unit to a sink node 106. A switch allocator 322 may forward the express flow control unit directly to the output link 306.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.